Semiconductor devices, e.g., , memory devices, etc., are generally provided with a delay circuit for adaptively delaying signals generated locally or for delaying externally-applied signals. Such a delay circuit has been used as a timing control component in semiconductor devices.
The delay circuit typically provided in this field has a chain configuration constructed of CMOS inverters, and resistances and capacitors. The delay chain uses an external or internal source voltage as an operating voltage. If the operating voltage increases, an amount of delay induced by such a delay chain is reduced based on a change of internal impedance, etc.
FIG. 1 depicts a delay circuit used with a semiconductor device, according to the Background Art. In FIG. 1, CMOS inverters INV1-INV4 are cascade-connected and represent four stages that constitute the delay chain. Each stage includes a CMOS inverter INVi, a capacitance unit Ci, and a resistance unit Ri. Resistance units R1, R3 are connected between each of odd-numbered CMOS inverters INV1, INV3 and a source voltage node, e.g., an externally-applied source voltage VEXT, respectively. Resistance units R2, R4 are each connected between each of even-numbered CMOS inverters INV2, INV4 and a node having ground voltage, respectively. Capacitance units C1, C3 are connected between VEXT and the outputs of odd-numbered CMOS inverters INV1, INV3, respectively. Capacitance units C2, C4 are connected between outputs of even-numbered CMOS inverters INV2, INV4 and a node having ground voltage, respectively.
Each of CMOS inverters INV1-INV4 functions as a unit delay. Resistance unit R1 and capacitance unit C1 together constitute another type of delay unit, namely an RC-type delay unit. Similarly, resistance unit R2 & capacitance unit C2, resistance unit R3 & capacitance unit C3 and resistance unit R4 & capacitance unit C4 constitute RC-type delay units, respectively.
An input signal IN that is provided at an input terminal is delayed by a delay operation of inverters INV1-INV4, resistance units R1-R4 and capacitance units C1-C4, and is then output at an output terminal as output signal OUT.
Operation of the Background Art delay chain of FIG. 1 will now be described. If a level of VEXT increases (due to any of various causes), current flowing through resistance units R1, R3 increases, and so the operating current of inverters INV1, INV3 increases. As such operating current increases, the delay times to complete the inverting operation (representing the delay times induced by inverters INV1, INV3) decrease, respectively.
Some types of apparatus can benefit from a delay chain's reduction in delay time associated with an increase in VEXT. For example, in a high-speed semiconductor memory device, operation of a sense amplifier (for sensing data of a memory cell) can cause a level of the array source voltage (which is the operating voltage applied to cells in a memory device) to drop momentarily. To prevent such a momentary drop in the array source voltage, the Background Art employs a scheme for adaptively overdriving an array source voltage generator (that generates the array source voltage) in which a control pulse is: generated in response to a sense amplifier enable signal; and is then passed through the delay circuit of FIG. 1. Accordingly, the width of the control pulse is reduced when the array source voltage increases, which reduces a degree to which the array source voltage generator is overdriven.